# Linux Kernel Module Cheat

##### 24.17.1.2. gem5 MinorCPU

Generic in-order superscalar core.

Its C++ implementation that can be parametrized to more closely match real cores.

Note that since gem5 is highly parametrizable, the parametrization could even change which instructions a CPU can execute by altering its available functional units, which are used to model performance.

For example, `MinorCPU` allows all implemented instructions, including ARM SVE instructions, but a derived class modelling, say, an ARM Cortex A7 core, might not, since SVE is a newer feature and the A7 core does not have SVE.

The weird name "Minor" stands for "M (TODO what is M) IN ONder".

Its 4 stage pipeline is described at the "MinorCPU" section of gem5 ARM RSK.

A commented execution example can be seen at: gem5 event queue MinorCPU syscall emulation freestanding example analysis.

There is also an in-tree doxygen at: `src/doc/inside-minor.doxygen` and rendered at: http://pages.cs.wisc.edu/~swilson/gem5-docs/minor.html

As of 2019, in-order cores are mostly present in low power/cost contexts, for example little cores of ARM bigLITTLE.

The following models extend the `MinorCPU` class by parametrization to make it match existing CPUs more closely:

- `HPI`: derived from `MinorCPU`.

  Created by Ashkan Tousi in 2017 while working at ARM.

  According to gem5 ARM RSK:

  > The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation.

- `ex5_LITTLE`: derived from `MinorCPU`. Description reads:

  > ex5 LITTLE core (based on the ARM Cortex-A7)

  Implemented by Pierre-Yves Péneau from LIRMM, which is a research lab in Montpellier, France, in 2017.