# Linux Kernel Module Cheat

#### 24.21.3. gem5 `MSHR`

Mentioned at: http://pages.cs.wisc.edu/~swilson/gem5-docs/gem5MemorySystem.html

Each cache object owns a `MSHRQueue`:

    class BaseCache : public ClockedObject
    {
        /** Miss status registers */
        MSHRQueue mshrQueue;

`BaseCache` is the base class of `Cache` and `NoncoherentCache`.

`MSHRQueue` is a `Queue` of `MSHR`:

    class MSHRQueue : public Queue<MSHR>

and Queue is also a gem5 class under `src/mem/cache/queue.hh`.

The MSHR basically keeps track of all information the cache receives, and helps it take appropriate action. I’m not sure why it is separate form the cache at all, as it is basically performing essential cache bookkeeping.

A clear example of MSHR in action can be seen at: gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs. In that example what happened was:

- CPU1 writes to an address and it completes

- CPU2 sends read

- CPU1 writes to the address again

- CPU2 snoops the write, and notes it down in its MSHR

- CPU2 receives a snoop reply for its read, also from CPU1 which has the data and the line becomes valid

- CPU2 gets its data. But the MSHR remembers that it had also received a write snoop, so it also immediately invalidates that line

From this we understand that MSHR is the part of the cache that synchronizes stuff pending snoops and ensures that things get invalidated.