# Linux Kernel Module Cheat

###### 24.21.2.1.1. gem5 `MemCmd`

Each gem5 `Packet` contains a `MemCmd`

The `MemCmd` is basically an enumeration of possible commands, stuff like:

    enum Command
    {
        InvalidCmd,
        ReadReq,
        ReadResp,

Each command has a fixed number of attributes defined in the static array:

    static const CommandInfo commandInfo[];

which gets initialized in the .cc file in the same order as the Command enum.

    const MemCmd::CommandInfo
    MemCmd::commandInfo[] =
    {
        /* InvalidCmd */
        { 0, InvalidCmd, "InvalidCmd" },
        /* ReadReq - Read issued by a non-caching agent such as a CPU or
         * device, with no restrictions on alignment. */
        { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" },
        /* ReadResp */
        { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },

From this we see for example that both `ReadReq` and `ReadResp` are marked with the `IsRead` attribute.

The second field of this array also specifies the corresponding reply of each request. E.g. the reply of a `ReadReq` is a `ReadResp`. `InvalidCmd` is just a placeholders for requests that are already replies.

    struct CommandInfo
    {
        /// Set of attribute flags.
        const std::bitset<NUM_COMMAND_ATTRIBUTES> attributes;
        /// Corresponding response for requests; InvalidCmd if no
        /// response is applicable.
        const Command response;
        /// String representation (for printing)
        const std::string str;
    };

Some important commands include:

- `ReadReq`: what the CPU sends out to its cache, see also: gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs

- `ReadSharedReq`: what dcache of the CPU sends forward to the gem5 crossbar interconnect after a `ReadReq`, see also: see also: gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs

- `ReadResp`: response to a `ReadReq`. Can come from either DRAM or another cache that has the data. On gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs we see that a new packet is created.

- `WriteReq`: what the CPU sends out to its cache, see also: gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs

- `UpgradeReq`: what dcache of CPU sends forward after a `WriteReq`